CSI_CLK_SEL=CSI_CLK_SEL_0, CSI_PODF=CSI_PODF_0
CCM Serial Clock Divider Register 3
| CSI_CLK_SEL | Selector for csi_mclk multiplexer 0 (CSI_CLK_SEL_0): derive clock from osc_clk (24M) 1 (CSI_CLK_SEL_1): derive clock from PLL2 PFD2 2 (CSI_CLK_SEL_2): derive clock from pll3_120M 3 (CSI_CLK_SEL_3): derive clock from PLL3 PFD1 |
| CSI_PODF | Post divider for csi_mclk. Divider should be updated when output clock is gated. 0 (CSI_PODF_0): divide by 1 1 (CSI_PODF_1): divide by 2 2 (CSI_PODF_2): divide by 3 3 (CSI_PODF_3): divide by 4 4 (CSI_PODF_4): divide by 5 5 (CSI_PODF_5): divide by 6 6 (CSI_PODF_6): divide by 7 7 (CSI_PODF_7): divide by 8 |